Junior Fellowship: Digital ASIC Design Engineer

Company Description

At CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world's largest and most complex scientific instruments, they study the basic constituents of matter - fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact, and provides insights into the fundamental laws of nature. Find out more on http://home.cern.

Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization.

Job Description

Are you an electronics designer with experience in digital design implementation and in Electronic Design Automation (EDA) tools and would you like to contribute developing CERN technologies and bringing them to other fields of science like medicine, biology or chemistry?

We are working on a family of Application Specific Integrated Circuits (ASICs) for the readout of fast detectors (SiPMs, MCPs) to precisely measure the time of arrival of particles to the detector.

We are opening a position for a digital electronics designer to strengthen our microelectronics design capabilities. You will contribute to the design a low power Time-To-Digital Converter with ~25ps time bin to be integrated with the already existing FastIC chip, developed in collaboration with the University of Barcelona. This project has been funded by the CERN Knowledge Transfer in view of its potential in the field of Medical Applications.

Qualifications

Eligibility criteria

• You are a national of a CERN Member or Associate Member State;
• You have graduated or are about to graduate (within six months from the date of the committee), with a university degree (BSc or MSc level) and have no more than 4 years’ relevant experience after obtaining your degree in the field of electronics engineering or a related field. Please note that experience prior to the latest obtained degree will not be considered for the calculation of your overall years of experience.

Essential skills and experience

• Good knowledge in the design and simulation of digital microelectronics circuits;
• You have experience with Cadence EDA physical implementation and verification tools;
• Development of synthesizable Verilog RTL code, physical implementation (RTL to GDS),  functional and physical verification of digital ASICs.

Desired skills and experience

• Experience in the use of low power design techniques in modern CMOS processes (130nm and below).

Please note that CERN Staff members are not eligible to apply for a Fellowship.

Additional Information

CERN would very much like to benefit from your expertise, commitment and passion. 

In return, CERN will provide you with:

• An employment contract for between six months (minimum) up to a maximum of 36 months.
• A stipend ranging from 5,305to 6,586 Swiss Francs per month (net of tax).
• Coverage by CERN’s comprehensive health scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
• Depending on your individual circumstances: an installation grant, family, child and infant allowances as well as travel expenses to and from Geneva.
• 2.5 days of paid leave per month.

Your Life @CERN

Get a glimpse of what it’s like to work at CERN: https://careers.cern/benefits and https://careers.cern/our-people

How to Apply:

You will need the following documents to complete your application:

• A CV (Resume) 
• Your most recent relevant qualification. (Degree)

We recommend you add two recent letters of recommendation, giving an overview of your academic and/or professional achievements. You can upload these letters at the time of application if you have them to hand. You will also be provided with a link as soon as you have submitted your application to forward to your referees to upload their letters confidentially. Please note this must be done before the closing date.

All applications should reach us no later than 27 January 2022.