Our team and mission

The Avionics & EEE Division is responsible for all aspects related to Avionics (with inputs from AOCS/GNC), Data Systems, Microelectronics, Flight Software and EEE Components and associated laboratory facilities. The responsibilities also extend to technology/product development and support to standardisation. 

More specifically TEC-ED responsibilities encompass:

• Definition of Avionics architecture (with inputs from AOCS/GNC) including procurement of associated products and supported through the Division’s following responsibilities:
  
  • On-board computer and Data Handling (PL/PF) for space systems, including their procurement and end-to-end validation (in close collaboration with TEC-EF);
  • Engineering of on-board software in all phases including pre-development and independent verification & validation of critical software, supporting software-system and functional engineering activities.
• Microelectronics and EEE Components:
  
  • Microelectronic devices and systems including development of radiation hardening techniques for such systems;
  • EEE Components both passive and active, including product development. Qualification, reliability and Radiation Hardness Assurance in support of TEC-Q;
  • Contribute to the European Space Component Coordination (ESCC) and all associated activities.
• Development and operation of a reference laboratory for components evaluation against the space environment (including radiation), reliability assessment, Data Systems, Microelectronics and Flight Software domains.

The Microelectronics Section (TEC-EDM) of the Data Systems, Microelectronics and Components Division (TEC-ED) core responsibilities cover technical support to ESA missions and research activities in the areas of:

(i) Digital and analogue integrated circuit: Application Specific Integrated Circuits (ASIC), Processors (CPU, GPU, VPU and accelerators), Field Programmable Gate Arrays (FPGA) and System-on-Chips (SoCs), as well as Intellectual Property (IP) Core developments for space applications;
(ii) Mitigation techniques against radiation effects for ASIC and FPGA;
(iii) Tools and methods for Integrated Circuit design and development (from specifications to tested devices).

Candidates interested are encouraged to visit the ESA website: http://www.esa.int  

Field(s) of activity for the internship

Topic of the internship: Evaluation of low-power RISC-V centric data signal processing units  

RISC-V is an open-source Instruction Set Architecture (ISA) that is at the centre of several on-going developments at ESA. A notable aspect of RISC-V’s design is its modular structure, which consists of base components and optional extensions. This flexibility allows for the creation of custom extensions tailored to the needs of specific applications, particularly on dedicated hardware accelerators. Several approaches to enhancing RISC-V processor computation exist, for instance Single Instruction, Multiple Data (SIMD) or vector extensions offer alternative ways to enhancing computation, each with their own strengths depending on the workload.

For high computationally demanding tasks—such as high-resolution data and image processing or artificial intelligence (AI) inference—hardware accelerators play a crucial role in boosting performance. Graphics Processing Units (GPUs), have demonstrated significant utility in accelerating a wide range of general purpose applications. In the context of space, low-power and radiation tolerance are generally demanded. Soft GPUs can provide a scalable solution as they can be mapped to space-grade Field-Programmable Gate Array (FPGA) target; examples relevant for space include Vortex GPU and GPU@SAT by and IngeniARS.

The primary objective of this activity is to evaluate the performance of soft-GPUs as accelerators within a RISC-V-centered SoC, and to compare them with other accelerator options such as SIMD or vector extensions. This will involve benchmarking soft-GPU performance using representative workloads, assessing integration strategies (e.g., loosely or tightly coupled architectures) by measuring metrics like latency and throughput, and analyzing which application domains map best to each accelerator type.

Behavioural competencies

Result Orientation
Operational Efficiency
Fostering Cooperation
Relationship Management
Continuous Improvement
Forward Thinking

For more information, please refer to ESA Core Behavioural Competencies guidebook

Education

You must be a university student, preferably studying at master’s level. In addition, you must be able to prove that you will be enrolled at your University for the entire duration of the internship.

Additional requirements

The working languages of the Agency are English and French. A good knowledge of one of these is required. Knowledge of another ESA Member State language is an asset.

During the interview, your motivation for applying to this role will be explored.

Microelectronics background, including digital integrated circuit modelling languages (e.g. VHDL, Verilog, SystemVerilog and SystemC) and computer aided design tools for digital design from e.g. Synopsys, Mentor and Cadence together with knowledge of processors and their toolchain for digital signal processing would be required.